文献阅读:01

标题:A New Opportunity for 2D van der Waals Heterostructures: Making Steep-Slope Transistors
作者:Juan Lyu, Jing Pei, Yuzheng Guo, Jian Gong and Huanglong Li
期刊:Advanced Materials
日期:2019

简介:这是一篇关于场效应晶体管的文献,标题为“二维范德华异质结的新机遇:制作陡坡晶体管”。大致翻译了一下,翻译仅供参考,请以原文为准。如翻译有不妥之处,欢迎一起讨论。

摘要

The use of a foreign metallic cold source (CS) has recently been proposed as a promising approach toward the steep-slope field-effect-transistor (FET). In addition to the selection of source material with desired density of states–energy relation (D(E)), engineering the source:channel interface for gate-tunable channel-barrier is crucial to CS-FETs. However, conventional metal:semiconductor (MS) interfaces generally suffer from strong Fermi level pinning due to the inevitable chemical disorder and defect-induced gap states, precluding the gate tunability of the barriers. By comprehensive materials and device modeling at the atomic scale, it is reported that 2D van der Waals (vdW) MS interfaces, with their atomic sharpness and cleanness, can be considered as general ingredients for CS-FETs. As test cases, InSe-based n-type FETs are studied. It is found that graphene can be spontaneously p-type doped along with slightly opened bandgap around the Dirac-point by interfacing with InSe, resulting in superexponentially decaying hot carrier density with increasing n-type channel-barrier. Moreover, the D(E) relations suggest that 2D transition-metal dichalcogenides and 2D transition-metal carbides are a rich library of CS materials. Graphene, Cd3C2, T-VTe2, H-VTe2, and H-TaTe2 CSs lead to subthreshold swing below 60 mV dec-1. This work broadens the application potentials of 2D vdW MS heterostructures and serves as a springboard for more studies on low-power electronics based on 2D materials.

最近,有人提出,使用外加金属冷源(cold source,CS)来实现陡坡场效应晶体管(field effect transistor,FET)是一种可行的方法。除了选择具有理想的态密度-能量关系(D(E))的源极材料之外,设计一种可通过栅极调控沟道势垒的源极-沟道界面对 CS-FET 也是至关重要的。然而,传统的金属-半导体(MS)界面通常因为不可避免的化学乱序和缺陷诱导的带隙态而遭受强费米能级钉扎的影响,妨碍了栅极对势垒的调控。综合各类原子尺度的材料和器件建模,有报道称,二维(2D)范德华(van der Waals,vdW) MS 界面具有原子级别清晰干净的表面,可以用来搭建 CS-FET。作为一个测试案例,作者研究了一种基于 InSe 的 n 型 FET。研究发现,石墨烯(graphene)与 InSe 构成界面后可以自发地形成 p 型掺杂,并且在狄拉克(Dirac)点打开了一个微小的带隙,导致其热载流子密度随着 n 型沟道势垒的上升而超指数级地降低。此外,D(E) 关系表明 2D 过渡金属二硫化物(transition-metal dichalcogenides)和 2D 过渡金属碳化物(transition-metal carbides)都是非常丰富的 CS 材料库。石墨烯、Cd3C2、T-VTe2、H-VTe2 和 H-TaTe2 这些冷源均可以使亚阈值摆幅降低至低于 60 mV dec-1。本工作拓宽了 2D vdW MS 异质结的应用潜质,为后续进一步研究基于 2D 材料的低功耗电子技术提供了支持。

前言

Propelling the current interest in electronics based on 2D materials is the continual discovery of new physical phenomena and the resultant device innovations.[1–4] Field-effect-transistor (FET) technology has been the workhorse of modern semiconductor industry. 2D semiconducting materials such as MoS2, black phosphorus, InSe, and PdSe2 have been widely studied as channel materials to replace bulk silicon because of the ideal electrostatic control of the atomically thin channels.[5–14] Another unique property of 2D materials is the ability to form vertical heterostructures by van der Waals (vdW) interactions without direct chemical bonding.[15–18] This offers considerable freedom in integrating various materials without the constraints of crystal lattice matching for unprecedented functions. In regard to FET devices, it has been predicted by theory and demonstrated by experiment that vdW metal:semiconductor (MS) source/drain-contacts outperform conventional contacts in achieving low contact resistance.[19–22] This has been attributed to the weak Fermi-level (FL) pinning effect because of the less chemical disorder and defect-induced gap states at the 2D vdW MS interfaces.

不断发现的新物理现象和由此产生的器件创新推动着当前人们对基于二维材料的电子技术的兴趣[1–4]。场效应晶体管(field effect transistor,FET)技术已经成为现代半导体工业的主力军。二维半导体材料,如 MoS2、黑磷(black phosphorus)、InSe 和 PdSe2 等,作为替代块体硅(bulk silicon)的沟道材料,其原子级厚度的沟道具有理想的静电控制性能,因此已经得到非常广泛的研究[5–14]。二维材料的另一个独特性质是,能够通过没有直接化学键连接的范德华(van der Waals,vdW)交互作用形成垂直的异质结[15–18]。这为拼接多种材料在一起而无需考虑晶格匹配的约束提供了可观的自由度。对于 FET 而言,有理论预测和实验证实 vdW 金属-半导体(MS)源-漏接触的模型在获得低接触电阻方面要更优于传统的接触模型[19–22]。这是由于 2D vdW MS 界面的化学乱序和缺陷诱导的带隙态较少,费米能级(Fermi-level,FL)钉扎较弱导致的。

The reinvention of the semiconductor device technology has been catalyzed by the limits of power dissipation.[23] Due to the thermionic limit, conventional FETs require at least 60 mV of gate voltage to increase the source–drain current by one order of magnitude at room temperature, precluding the continuous scaling of the supply voltage and the decrease of power consumption.[24,25] Various device innovations have been proposed to lower the subthreshold swing (SS) below 60 mV dec−1.[26,27] Tunneling FET (T-FET) by using heterojunction-channel and negative-capacitance FET (NC-FET) by using ferroelectric-gateoxide are most extensively studied.[28–31] However, T-FETs have now been well known for low on-current; meanwhile, NC-FETs can often suffer from large hysteresis. Recently, cold source (CS) has emerged as a promising solution to overcome the limitations of T-FETs and NC-FETs. In a CS-FET, the hot carrier (HC) density of states (DOSs) of the CS should decrease with increasing channel barrier.[32] The function of the CS can be understood by referring to the Landauer–Buttiker formula
$$I = \frac{2e}{h} \int_{-\infty}^{\infty} T(E) D(E) [f(E-E_{F}(S)) - f(E-E_{F}(D))]\ \mathrm{d}E$$
where $T(E)$ is the transmission probability; $D(E)$ is the DOS; $f(E)$ is the Fermi–Dirac distribution function; $E_{F}(S)$ and $E_{F}(D)$ are the Fermi levels of the source and drain, respectively. In a conventional n-type FET, in the ON state, electrons are injected from the highly n-type doped (degenerate) semiconducting region whose conduction band DOS is an increasing function of energy, or from normal metal whose DOS is essentially independent of energy. In the OFF state, due to the thermal Boltzmann distribution, electrons in the source have an energy distribution ($n(E) = D(E) × f(E)$) that spreads (thermal tail) to a value exceeding the potential barrier (hot electrons). Due to the nondecreasing D(E) relationship, the hot electron density can increase with energy, which sets a 60 mV dec−1 limit on SS. However, if injection is from a material whose HC DOS decreases with increasing channel barrier, superexponentially decreasing HC density (n(E)) can be achieved, leading to more localized carrier distribution around the FL without a long thermal tail above the channel barrier. As a result, the device can be switched-off faster because the thermal tail can be more effectively cut off by D(E) according to the above formula, thus breaking the SS limit of the conventional FETs.

器件功耗的限制不断地推动着半导体器件技术的再创造[23]。由于热离子的限制,要使传统 FET 在室温下的源-漏电流增加一个数量级至少需要 60 mV 的栅极电压,这一限制使电源电压难以连续变化,也使功耗难以降低[24,25]。迄今人们提出了多种多样的新型器件,以期将亚阈值摆幅(subthreshold swing,SS)降低至 60 mV dec−1以下[26,27]。其中,使用异质结沟道的隧穿 FET(T-FET)和使用铁电栅氧化物的负电容 FET(NC-FET)得到了最为广泛的研究[28–31]。然而,众所周知,T-FET 的开态电流较低,同时 NC-FET 也会经常受到较大的磁滞现象的影响。近日,冷源(cold source,CS)技术已成为一种可以克服 T-FET 和 NC-FET 的局限性的有前景的解决方案。在 CS-FET 中,冷源的热载流子(hot carrier,HC)态密度(density of states,DOS)理应随着沟道势垒的增大而减小[32]。冷源的作用可以参考 Landauer–Buttiker 公式来理解:
$$I = \frac{2e}{h} \int_{-\infty}^{\infty} T(E) D(E) [f(E-E_{F}(S)) - f(E-E_{F}(D))]\ \mathrm{d}E$$
其中 $T(E)$ 是透射率,$D(E)$ 是 DOS,$f(E)$ 是费米-狄拉克(Fermi–Dirac)分布函数,$E_{F}(S)$ 和 $E_{F}(D)$ 分别是源极和漏极的费米能级。传统的 n 型 FET 在开态时,电子从导带 DOS 随能量增加而增大的高 n 型掺杂(简并)半导体区域注入,或者从 DOS 基本上与能量无关的正常金属注入。在关态时,由于热玻尔兹曼(Boltzmann)分布,源极的电子具有一定的能量分布($n(E) = D(E) × f(E)$),该分布(热尾)延展至一个超过势垒(热电子)的值。由于非衰减 $D(E)$ 关系,热电子密度会随着能量而增加,这给 SS 设置了一个 60 mV dec−1 的限制。然而,如果注入的电子来自于 HC DOS 随着沟道势垒的增加而减小的材料,就可以获得超指数级降低的 HC 密度($n(E)$),从而导致在沟道势垒上方没有长热尾的情况下,FL 附近有更加局域的载流子分布。因此,根据上述公式,由于 $D(E)$ 可以更加有效地切断热尾,这个器件可以更快地关闭,从而打破传统 FET 中的 SS 限制。

In addition to the desired DOS–energy relation (D(E)) of the source material, source:channel interface with weak FL pinning is crucial to a CS-FET. In fact, the gate-tunability of the channel barrier distinguishes a CS-FET from conventional Schottky-barrier (SB)-FET where the FL of the MS interface is pinned and the barrier height can hardly be tuned by the gate-voltage.

除了源极材料需要具备理想的态密度-能量关系之外,源极-沟道的界面内较弱的 FL 钉扎对 CS-FET 同样也是至关重要的。事实上,我们可以通过沟道势垒的栅极可调控性来区分 CS-FET 和 传统的肖特基势垒(Schottky barrier,SB) FET,其中传统 FET 的 MS 界面 FL 被钉扎住了,其势垒高度很难通过栅极电压来调整。

Considering that 2D vdW MS heterostructures show weak FL pinning and enable effective tuning of the SBs, we investigate in this work the feasibility of using such unique heterostructures as general ingredients for CS-FETs. As test cases, monolayer InSe-based n-type high-mobility FETs with prospective 2D CSs are studied. By analyzing the D(E) relation, we find that, in addition to graphene, 2D transition-metal dichalcogenides (TMDs) and 2D transition-metal carbides (MXene) are a rich library of CS materials. Pristine graphene, doped graphene, Cd3C2, T-VTe2, H-VTe2, and H-TaTe2 CSs are found to result in SS below 60 mV dec−1, which can be explained by their desired HC distributions and the gate-tunable source:channel barrier heights. This work opens up new opportunities at the confluence of 2D materials and electronics.

考虑到 2D vdW MS 异质结具有较弱的 FL 钉扎,能够有效地调节 SB,这项工作的作者探究了使用这种独特的异质结来搭建 CS-FET 的可行性。作为测试案例,作者研究了具有前瞻性的 2D CS,基于单层 InSe 的 n 型高迁移率 FET。通过分析 $D(E)$ 关系,作者发现,除了石墨烯之外,2D 过渡金属二硫化物(transition metal dichalcogenide,TMD)和 2D 过渡金属碳化物(transition-metal carbide,MXene)都是非常丰富的 CS 材料库。研究发现,原始的石墨烯、掺杂的石墨烯、Cd3C2、T-VTe2、H-VTe2 和 H-TaTe2 这些冷源均可以使 SS 降低至低于 60 mV dec-1,这些可以通过它们理想的 HC 分布和栅极可调的源极-沟道势垒高度来解释。这项工作为 2D 材料和电子技术的融合开辟了新的机遇。

图表

<div><q>
<b>Figure 1</b>. a) Side view of n-type InSe-based graphene CS-FET. The equivalent-oxide-thickness (EOT = 0.54 nm), gate length (L = 7.8 nm), and supply voltage (V<sub>SD</sub> = 0.74 V) are parametrized according to the International Technology Roadmap of Semiconductors (ITRS)<sup>[36]</sup> for high performance transistors in 2021. b) Band structure of InSe:graphene heterojunction. The electronic states contributed by graphene and InSe are marked by the red and black curves, respectively. The Fermi energy is set to zero. The inset shows the relaxed atomic structure, and the yellow, pink, and gray balls represent In, Se, and C atoms, respectively. c) Transfer characteristics of InSe-based FETs with and without graphene source.
</q></div><div>
<b>图 1</b>. a)基于 InSe 的 n 型石墨烯 CS-FET。根据 2021 年高性能晶体管国际半导体技术路线图(ITRS)<sup>[36]</sup>的要求,设置等效氧化层厚度(equivalent oxide thickness,EOT = 0.54 nm),栅极长度(length,L = 7.8 nm)以及电源电压(supply voltage,V<sub>SD</sub> = 0.74 V)。b)InSe-石墨烯异质结的能带结构。红色和黑色曲线分别表示由石墨烯和 InSe 贡献的电子态。费米能级设置为零。插图展示了弛豫后的原子结构,其中黄色、粉色和灰色小球分别表示 In、Se 和 C 原子。c)基于 InSe 的 FET 在有或无石墨烯源时的传输特性。
</div>

<div><q>
<b>Figure 2</b>. DOSs projected to graphene CS-FET along the transport direction for a) ON-state and b) OFF-state devices. c) Transmission spectrums for ON and OFF states. d) Atomic DOSs projected to graphene source, InSe in the channel, and InSe in the drain for the ON- and OFF-state devices. e) Zoomed-in $DOS(E)$ and $n(E)$ in the energy region near which the steepest slope of SS = 51 mV dec<sup>−1</sup> occurs. For comparison, the linearly scaled Boltzmann distribution function $f(E)$ that equals $n(E)$ at the FL is shown in blue curve.
</q></div><div>
<b>图 2</b>. 石墨烯 CS-FET 在 a)开态和 b)关态时沿着传输方向的投影 DOS 图。c)开态和关态时的透射谱。d)器件在开态和关态时投影至石墨烯源、沟道中 InSe 以及漏极中 InSe 原子上的 DOS 图。e)在 SS = 51 mV dec<sup>−1</sup> 坡度最陡的位置附近放大 $DOS(E)$ 和 $n(E)$ 的能量区域。为了比较,图中用蓝色曲线标展现与 FL 处的 $n(E)$ 相等的线性缩放的玻尔兹曼分布函数 $f(E)$。
</div>

<div><q>
<b>Figure 3</b>. $DOS(E)$ and $n(E)$ relations of a) Zn<sub>3</sub>C<sub>2</sub>, b) Hg<sub>3</sub>C<sub>2</sub>, c) Cd<sub>3</sub>C<sub>2</sub>, d) T-VTe<sub>2</sub>, e) H-VTe<sub>2</sub>, and f) H-TaTe<sub>2</sub>.
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<b>图 3</b>. a)Zn<sub>3</sub>C<sub>2</sub>、b)Hg<sub>3</sub>C<sub>2</sub>、c)<sub>3</sub>C<sub>2</sub>、d)T-VTe<sub>2</sub>、e)H-VTe<sub>2</sub> 和 f)H-TaTe<sub>2</sub> 的 $DOS(E)$ 和 $n(E)$ 关系。
</div>

<div><q>
<b>Figure 4</b>. a) Band structure of InSe/T-VTe<sub>2</sub> heterojunction. The electronic states contributed from monolayer InSe and T-VTe<sub>2</sub> are marked by black and gray lines, respectively. The inset shows the relaxed atomic structure, and the green and orange balls represent V and Te atoms, respectively. b) Transfer characteristics of CS-FET with and without T-VTe<sub>2</sub> source.
</q></div><div>
<b>图 4</b>. a)InSe/T-VTe<sub>2</sub> 异质结的能带结构。黑色和灰色的线分别表示由单层 InSe 和 T-VTe<sub>2</sub> 贡献的电子态。插图展示了弛豫后的原子结构,其中绿色和橙色小球分别代表 V 和 Te 原子。b)CS-FET 在有或无 T-VTe<sub>2</sub> 源时的传输特性。
</div>

<div><q>
<b>Figure 5</b>. PLDOS of T-VTe<sub>2</sub> CS-FET, a) ON state and b) OFF state. c) Comparison of transmission spectrums for ON and OFF states. d) Atomic DOSs projected to T-VTe<sub>2</sub> as the source, InSe in the channel, and InSe in the drain in the ON and OFF states of the device, respectively. e) Zoomed-in DOS(E) and n(E) in the energy region near which the steepest slope of SS = 57 mV dec<sup>−1</sup> occurs.
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<b>图 5</b>. T-VTe<sub>2</sub> CS-FET 在 a)开态和 b)关态时的 PLDOS。c)开态和关态时透射谱的对比。d)器件在开态和关态时投影至 T-VTe<sub>2</sub> 源、沟道中 InSe 以及漏极中 InSe 原子上的 DOS 图。e)在 SS = 57 mV dec<sup>−1</sup> 坡度最陡的位置附近放大 $DOS(E)$ 和 $n(E)$ 的能量区域。
</div>

结论

The application potentials of 2D vdW MS heterostructures in steep-slope CS-FETs have been studied. According to the DOS(E) relations and the nonchemical natures of the interlayer interactions of various 2D metallic materials, such as graphene, the selected TMDs and MXenes, we anticipate that a plethora of 2D vdW materials can serve as the desired CS materials. As test cases, high-mobility monolayer InSe-based n-type FETs with pristine graphene, doped graphene, Cd3C2, T-VTe2, H-VTe2, and H-TaTe2 CSs have been investigated. These FETs show low SS values below 60 mV dec−1. The suppression of thermal tail contribution to the OFF current has been attributed to the gate-tunable channel barriers as well as the superexponentially decreasing n(E). DOS engineering for steep-slope, low off-current and high on-current CS-FETs, and exploring materials that enable polymorphic integration of metal–semiconductor heterophase homojunction for CS-FETs could be key research opportunities in the future. This work provides new opportunities for low-power electronics based on 2D materials.

本文研究了 2D vdW MS 异质结在陡坡 CS-FET 中的应用潜质。根据各种 2D 金属材料,如石墨烯、所选择的 TMD 和 MXene 等的 $DOS(E)$ 关系以及层间非化学性质的相互作用,作者预测大量的 2D vdW 材料可以作为理想的 CS 材料。作为测试案例,作者研究了基于单层 InSe,使用原始石墨烯、掺杂石墨烯、Cd3C2、T-VTe2、H-VTe2 和 H-TaTe2作为 CS 的高迁移率 n 型 FET。这些 FET 展现了低于 60 mV dec−1 的 SS 值。热尾对关态电流的抑制主要归因于栅极可调的沟道势垒以及超指数下降的 $n(E)$。陡坡、低关态电流和高开态电流 CS-FET 的 DOS 工程,以及探索拥有多种组合方式的金属-半导体异质相同质结材料以用于 CS-FET 可能是未来研究机遇的关键。这项工作为基于 2D 材料的低功耗电子激素提供了新的机遇。

文章作者: 喵函数
文章链接: https://eigenmiao.site/2020/03/04/article-01/
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